The present invention relates to a charge-coupled device (CCD) type solid state image pickup device, and more particularly, to a CCD-type solid state image pickup device in which an overflow drain (OFD) is formed around the surface of the semiconductor substrate.
A solid state image pickup device forms a pickup area where a solid element having a photoelectric conversion function and a signal accumulating function is utilized as one pixel. The signal charge accumulated in each pixel is converted into an electrical signal so that external image data detected by a multiplicity of pixels can be converted into an electrical signal.
Solid state image pickup devices typically use one of two signal scanning methods, an X-Y addressing system or a signal transfer system. According to the X-Y addressing system, the signal charge of each pixel is selectively read to obtain an output. A MOS-type solid state image pickup is a commercially available example of a device using the X-Y addressing method. According to the signal transfer system, the signal charge of each pixel is converted into an analog signal which is transferred to elements outside the pixel and serially read with analog signals associated with other pixels. A CCD-type solid state image pickup is one example of a device using the signal transfer method.
A CCD-type solid state image pickup can be further divided into two types, depending upon the transfer method used. A CCD-type solid state image pickup may use a frame transfer system, which includes an image sensing area for converting incident light into a signal charge, an accumulator for accumulating the signal charge, and a vertical transfer CCD for vertically conveying the signal charge. Alternatively, a CCD-type solid state image pickup may use an interline transfer system, which includes a photo-sensitive well for generating a signal charge in accordance with the strength of incident light, a vertical transfer CCD for vertically conveying the signal charge, a horizontal transfer CCD for horizontally conveying the signal charge conveyed from the vertical transfer CCD, and an output circuit portion for detecting the signal charge conveyed from the horizontal transfer CCD.
FIG. 1 is a diagram of a conventional CCD-type solid state image pickup using the interline transfer system.
Referring to FIG. 1, mask patterns 10 each form a photo-electric conversion region, i.e., a photo-sensitive well. Mask patterns 11 are interspersed between mask patterns 10, and each mask pattern 11 forms a channel region of a vertical transfer CCD. Each of mask patterns 13 forms a first transfer electrode of the vertical transfer CCD. Each of mask patterns 14 forms a second transfer electrode of the vertical transfer CCD. Mask pattern 12 forms a transfer channel for transferring the signal charge of a photo-electric conversion region to the vertical transfer CCD. Mask pattern 12 is disposed between mask patterns 10 and 11 and overlaps mask pattern 13. The mask patterns which form the horizontal transfer CCD and output circuit portion around the pixel cell array are not shown here.
A photo-shield film will be shown hereinafter, but is not shown in FIG. 1. FIG. 2 is a section view taken along line II--II of FIG. 1.
As shown in FIG. 1 and FIG. 2, the CCD-type solid state pickup employing an interline transfer system includes a P type well 38 formed in an N type semiconductor substrate 37. Photo-sensitive N type well 40 is formed in the P type well and accumulate a signal charge in response to incident light. N type channel region 41 of the vertical transfer CCD transfers the signal charge conveyed from the photo-sensitive well 40 to the horizontal transfer CCD and is formed vertically (refer to mask pattern 11 of FIG. 1) between separate photo-sensitive wells 40. Transfer channel 42 transfers the signal charge accumulated in the photo-sensitive well 40 to the N type channel region 41 of the vertical transfer CCD. First transfer electrodes 43 of the vertical transfer CCD receive a pulse for transferring the signal charge accumulated in a photo-sensitive well 40 to the vertical transfer CCD and a pulse for subsequently transferring the signal charge transferred from the photo-sensitive well 40 to the horizontal transfer CCD. A second transfer electrode (refer to mask pattern 14 of FIG. 1) of the vertical transfer CCD receives the pulse for subsequently transferring the signal charge transferred from the photo-sensitive well 40 to the horizontal transfer CCD. A horizontal transfer CCD (not shown) is formed in the horizontal direction around a pixel cell array and transfers the signal charges transferred from a plurality of vertical transfer CCDs to an output circuit (not shown). The output circuit outputs the signal charge transferred from the horizontal transfer CCD.
Referring to FIG. 2, reference numeral 36 denotes a channel stopper layer for separating each cell, 45 denotes an insulating film, and 46 denotes a photo-shield film.
In operation, when visible light is irradiated onto photo-sensitive well 40, an electrical signal charge is generated by the photon effect. The accumulated signal charge is proportional to the intensity of the irradiated light. During a field shift, the signal charge is transferred from photo-sensitive well 40 to channel region 41 via transfer channel 42 formed between photo-sensitive well 40 and channel region 41 of the vertical transfer CCD.
Next, the signal charge is conveyed from channel region 41 to the horizontal transfer CCD (not shown) by a clock pulse applied to first transfer electrodes 43 and the second transfer electrodes (mask pattern 14 shown in FIG. 1). The horizontal transfer CCD (not shown) is formed in the end of channel region 11 of the vertical transfer CCD. The signal charge is then transferred to an output circuit portion in the same manner, where it is detected as a voltage level.
However, in this solid state image pickup, there is a limit to the amount of signal charge that can be accumulated into the potential well corresponding to each photo-sensitive well. Specifically, when high-intensity visible light is irradiated onto the solid state image pickup, the signal charge generated in proportion to the intensity of the visible light may exceed the accumulation capacitance of the potential well and leak out. Such leakage may cause a blooming phenomenon in which the picture of a highlight portion is extended. If the signal charge flows into the adjacent vertical and horizontal transfer CCD, a smear phenomenon occurs. To prevent these phenomena, excess signal charge should be periodically discharged to an external circuit.
There have been various methods proposed for discharging the extra signal charge to an external circuit, including a CCD-type solid state image pickup where the vertical overflow drain (OFD) is formed beneath the photo-sensitive well (see Eiji Oda et al., "Blooming Suppression Mechanism for an Interline CCD Image Sensor with a Vertical Overflow Drain," IEDM 1983, pp 501-504).
FIG. 3 is a sectional view of a CCD-type solid state pickup corresponding to FIG. 2 which has a PNPN OFD structure (see Junichi Hojo et al., "A 1/3-inch 510(H).times.492(V) CCD Image Sensor with Mirror Image Function," IEEE Trans-electron Device, Vol. 38, No. 5, May 1991, pp 954-959).
As shown in FIG. 3, the CCD-type solid state image pickup having the above-described overflow drain structure includes a P.sup.- type first well 58 formed toward the surface of a N- type semiconductor substrate 57 which serves as an overflow barrier to suppress blooming. Photosensitive N type well 60 is formed on the surface of the first well 58 so as to accumulate the signal charge excited by incident light. P.sup.+ type dark-current suppressing layer 59 is formed by implanting high concentration boron ions to a photo-sensitive well and reduces dark-current, suppresses blooming, and enables the realization of a variable speed electronic shutter. N type channel region 61 of a vertical transfer CCD transfers a signal charge from the photo-sensitive well to a horizontal transfer CCD. P type second well 55 is formed beneath the channel region. Transfer channel 62 transfers the signal charge accumulated in the photo-sensitive well to an N type channel region of a vertical transfer CCD. A channel stopper layer 56 separates each cell. Photo shield film 66 is formed on a semiconductor substrate of the region where a photo-sensitive well is not formed. First transfer electrode 63 receives a pulse for transferring the signal charge accumulated in a photo-sensitive well to a vertical transfer CCD and a pulse for subsequently transferring the signal charge to a horizontal transfer CCD. A second transfer electrode (not shown) receives the pulse for subsequently transferring the signal charge to a horizontal transfer CCD. A horizontal transfer CCD (not shown) is formed around a pixel cell array and transfers the signal charge transferred from a plurality of vertical transfer CCDs to an output circuit (not shown), which outputs the signal charge transferred from the horizontal transfer CCD.
FIG. 4 shows the distribution of electric potential on line IV--IV of FIG. 3.
In operation, when visible light is irradiated onto photo-sensitive well 60, a signal charge, i.e., electrons excited in proportion to the incident light energy, is accumulated in the photo-sensitive well. When the signal charge accumulated in the potential well of the photo-sensitive well 60 exceeds the accumulation capacity of the photo-sensitive well, the signal charge flows towards the semiconductor substrate 57 only after going over the potential barrier of P.sup.- type first well 58. Thus, signal charge flow into the photo-sensitive well environment and transfer CCD is prevented.
When semiconductor substrate 57 acts as a drain against overflow, the distribution of the electric potential on line IV--IV of FIG. 3 according to an overflow operation voltage V.sub.OFD applied to N.sup.- type semiconductor substrate 57 is as shown by the solid line in FIG. 4.
Referring to FIG. 5, the amount of signal charge optically excited and accumulated in the photo-sensitive well is, until overflow occurs, proportional to the intensity of the irradiated light. Once overflow occurs, the amount of signal charge is held constant. Accordingly, blooming and smears can be prevented since the excessive signal charge flows toward semiconductor substrate 57 instead of toward the adjacent photo-sensitive well, the transfer CCD, etc.
In a conventional solid state image pickup, the time period for signal charge accumulation is equal to one field period (16.7 ms). To improve the resolution for fast-moving subjects, the signal charge accumulating time period has to be kept shorter than one field period. Accordingly, it has been proposed to control the signal charge accumulation time period in a solid state pickup by a variable speed shutter (see U.S. Pat. Nos. 5,014,132 (Title; CCD Image, Inventor; Kumesama, Tetsuro, application No. 383,179), 5,045,906 (Title; SOLID STATE IMAGE PICKUP DEVICE HAVING PHOTO-ELECTRIC CONVERTING REGION VIA SCHOTTKY BARRIER, Inventor; Kazuhisa Nagaya, application No. 559,035) and 4,875,100 (Title; ELECTRONIC SHUTTER FOR A CCD IMAGE SENSOR, Inventor; Kazuya Yonemoto et al, application No. 110,844)).
As described in U.S. Pat. No. 4,875,100, when an electronic shutter voltage is applied to the N.sup.- type semiconductor substrate 57, the distribution of the electric potential, illustrated by the dotted line of FIG. 4, depends on the applied shutter voltage (.DELTA.V.sub.SHT). In this manner, all signal charges accumulated in the potential well may be removed.
FIG. 6 is a simple timing diagram of an electronic shutter operation. In general, the time period for accumulating the signal charge into a photo-sensitive well is equal to one field period, i.e., 1/60th of a second. When an electronic shutter operates such that shutter voltage pulses having an amplitude of .DELTA.V.sub.SHT are continuously added to an OFD operation voltage (V.sub.OFD) level over a time T.sub.0, the signal charge is accumulated for the period of 1/60-T.sub.0 seconds. Thus, the amount of the accumulated charge can be controlled.
A CCD-type solid state image pickup having the conventional OFD structure has the following problems. First, N.sup.- type semiconductor substrate 57 which performs a vertical-type OFD operation is formed by low-concentration impurity implantation. Accordingly, when an OFD operation is to be performed, a high voltage must be applied to the semiconductor substrate. Second, when a shutter operation is performed in a vertical-type OFD structure, a high-voltage shutter pulse is also needed in order to control the potential barrier of P.sup.- type first well 58. Third, since the N.sup.- type semiconductor substrate which performs an OFD operation is formed throughout the whole chip, on-chip circuit realization is difficult when additional PMOS and CMOS circuits are to be formed outside the image sensing area of a solid state image pickup.